OUR DIRECTION & PHILOSOPHY
SeedCore is the open trust runtime for affordable physical AI: browser-first robot experiments, canonical Central World assembly authoring, bounded execution authority, and verifiable action evidence.
Small robot bodies make compact, supervised experiments practical. Lower mass can reduce collision energy, but actuator torque, pinch points, speed, power rails, and the workspace still need evaluation. SeedCore starts with simulation and explicit limits; physical safety requires measured qualification of each build.
AI agents and vision-language models propose actions that affect workspaces, hardware, and network services. SeedCore makes permission and evidence explicit through single-use session tokens, revocation fencing, watchdog bounds, and tamper-evident receipts. The delivered rehearsal exercises these controls in host simulation; a token or verified receipt does not establish physical safety.
THE TRUST LIFECYCLE
How SeedCore separates offline proxy authoring, policy admission, bounded session execution, and receipt verification.
Authors a canonical seedcore.assembly.v2 graph (CW-A01–A03) or proposes a bounded ActionIntent chunk with velocity, angle, and horizon limits.
The session rehearsal checks authority, profile bounds, and freshness before issuing a single-use token. Separately, the offline authoring store increments authorityEpoch on content changes and keeps admission null; live assembly admission is a later integration gate.
Executes bounded fast-spine-v1 simulation sessions (or target MCU interpolation once CW-D01/G1 pass) with independent watchdog fencing.
Validates session tokens, signer provenance, and action-bound receipts, quarantining missing, stale, or conflicting telemetry.
Authoring revisions and simulation rehearsals never grant physical hardware authority (physical_acceptance: false). Captured hardware evidence requires an enrolled device signer (G2).
THE OPERATING FOUNDATION
Every layer is designed for deterministic reproducibility, explicit scope labels, and open mathematical verifiability.
Analytically derived Lagrange dynamics with mass, Coriolis, gravity, and torque terms compiled to 13,242-byte dual-ABI WebAssembly. Powers 2D lessons (SIM-1/2) and the 1/2/3-link 3D Tree Studio (SIM-3, 78/78 tests passing).
12 byte-pinned .sc-part.json draft records (CW1, 107 tests) and the seedcore.assembly.v2 contract (CW-A01 v2, 117 Python + 71 Node tests) with RFC 8785 seedcore.jcs-safe-integers.v1 cross-language canonical bytes.
CW-A02/A03)
Offline authoring shell (ts/apps/mini-studio & ts/packages/robot-canvas) with duplicate-key JSON rejection, 32-entry / 2 MiB frozen revision store, deterministic undo/redo, stale-load fencing, and Three.js box-proxy preview, plus 15 mm candidate snapping, ghost previews, numeric placement, and subtree reparenting (88 TS tests, 14 API tests, 18 browser groups across CW-A02/A03).
M0
Pinned Microduck 0.1.0 MJCF package (64 Python tests passed, 24 skipped in the recorded workbench baseline), read-only microduck-sim-v1 HAL adapter (61 obs / 14 actions / 15 channels), and 16 upstream-derived observation/ONNX (alpha_walking.onnx) replay goldens.
CW-D01
Delivered fast-spine-v1 wire schemas, localhost split-screen bounded-session rehearsal, firmware packet preparer, and the Oct 19 M0 / CW-D01 candidate register (ESP32-S3-DevKitC-1-N8R8 & STS3215 spec A/0).
Token, signature, session receipt, and replay verification across Python and the Rust proof kernel (ee00f9c). Rejects expired, forged, replayed, revoked, and out-of-scope attempts.
TRANSPARENT ROADMAP & RELEASE GATES (G0–G5)
We strictly distinguish delivered software/simulation candidates from open hardware, firmware, and physical stopping gates.
SIM-1–SIM-3: 2D planar lab and 3D Tree Studio (78 Node + 30 native/Wasm invariant groups).
Central World CW1 & CW-A01–A03: 12 draft .sc-part.json parts, seedcore.assembly.v2 contract (117 Python + 71 Node tests), and offline immutable authoring with proxy snapping and numeric placement (88 TS tests, 14 API tests, 18 browser groups).
Simulation-First M0: Read-only Microduck profile, 16 ONNX goldens, split-screen fast-spine-v1 rehearsal, and Python/Rust receipt checks.
CW-A04 & CW-D01)
CW-A04 next: A pure DRC/net worker and unknown-aware BOM (CW-DRC-01–03), following the delivered CW-A03 proxy placement slice.
M0 / CW-D01 & M1–M2: Reconcile STS3215 A/0 page 4 vs. page 8 connector numbering and 4–7.4 V rail ratings during the 26 Oct–1 Nov qualification window, close independent Microduck training parity (M1), and advance live native M2 sessions.
CW-S/G/L & G1–G5)
CW-S01–S04: Restricted assembly-to-MJCF compiler, browser MuJoCo worker (mjswan 0.11.9 conditional assessment complete), and Robot Moments gestures.
CW-G/E/F/L & G1–G5: Live admission/replay, Build Pack exporter, conditional CW-F01/F02 ESP32-S3 NVS/firmware qualification (1 servo → 3 servos), and January authoring/simulation alpha review.
Grounded in SeedCore’s 18-month execution plan (Q4 2026–Q1 2028), Central World delivery schedule, and simulation-first acceptance record. Updated October 19, 2026.
JOIN THE EXPERIMENT
Whether you are authoring a proxy assembly, testing safe-by-physics control contracts, or reviewing hardware qualification gates, our open-source tools and trust runtime are built for you.